1. Field of the Invention
The present invention relates to a memory device and manufacturing method thereof. More particularly, the present invention relates to a non-volatile memory device and method of manufacturing the same.
2. Description of the Related Art
Electrically erasable programmable read-only memory (EEPROM) is a non-volatile memory device that allows multiple data writing, reading, and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment. A typical EEPROM device has a floating gate and a control gate fabricated using doped polysilicon. During a programming operation, electrons injected into the floating gate will be evenly distributed over the entire polysilicon floating gate layer. Obviously, if the tunneling oxide layer underneath the polysilicon floating gate contains some defects, a leakage current will be produced and reliability of the device will be affected.
To resolve the leakage problem in an EEPROM device, the polysilicon floating gate of a conventional memory device is replaced by a charge-trapping layer. The charge-trapping layer is a silicon nitride layer with silicon oxide layers above and below the silicon nitride layer, thereby creating an oxide/nitride/oxide (ONO) composite stacked structure. An EEPROM having this stacked gate structure is often referred to as a silicon/oxide/nitride/oxide/silicon (SONOS) memory device.
FIG. 1 is a cross-sectional view of a conventional SONOS memory device. As shown in FIG. 1, an oxide/nitride/oxide (ONO) composite layer 102 is formed over a substrate 100. The ONO composite layer 102 includes a bottom oxide layer 104, a silicon nitride layer 106 and a top oxide layer 108. In addition, a polysilicon gate 112 is formed over the ONO composite layer 102 to serve as a word line. A source/drain region 118 is formed in the substrate 100 on each side of the ONO composite layer 102 to serve as a buried bit line. Spacers 116 are also formed on the sidewalls of the polysilicon gate 112. A lightly doped region 114 is formed in the substrate 100 underneath the spacers 116 to connect with the source/drain region 118 electrically.
In general, the SONOS memory device is programmed by injecting channel hot electrons (CHE) through the bottom oxide layer 104 and trapping the electrons within the ONO composite layer 102. Furthermore, data within the SONOS memory device is erased by injecting tunneling enhanced hot holes (TEHH) through the bottom oxide layer 104 and annulling the trapped electrons inside the ONO composite layer 102. The storage capacity of a SONOS memory device mainly depends on the coupling ratio. In other words, the contact area between the aforementioned top oxide layer 108 and the polysilicon gate 112.
Through the widespread miniaturization of semiconductor devices, line width of each device is shrunk correspondingly. When the contact area between the top oxide layer and the polysilicon gate inside the SONOS memory device is reduced, overall storage capacity is affected. Consequently, scientists and engineers are now working hard to find methods for increasing the coupling ratio and hence boosting the storage capacity of a SONOS memory device.